Momentum Builds on RISC-V European Adoption
EU funding model needs more industrial focus.
By Pablo Valerio, EETimes | June 9, 2025
Paris – As the RISC-V Europe Summit convened in Paris, the open standard instruction set architecture (ISA) continued its march towards mainstream adoption, sparking discussions among European experts about the continent’s role, its unique strengths, and persistent challenges.
In an exclusive interview for EETimes, Teresa Cervero of the Barcelona Supercomputing Center and Stefan Wallentowitz from Munich University of Applied Sciences, members of the RISC-V Summit Europe steering committee, offered their perspectives from the heart of European academia and research, areas instrumental in fostering the early growth of RISC-V.
To read the full article, click here
Related Semiconductor IP
- RISC-V IOPMP IP
- RISC-V Debug & Trace IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- 64-bit RISC-V core with in-order single issue pipeline. Tiny Linux-capable processor for IoT applications.
- Tiny, Ultra-Low-Power Embedded RISC-V Processor
Related News
- CEO interview: Globalfoundries' Tom Caulfield on the European project
- Hewlett Packard Enterprise and SiPearl Partner to Develop HPC Solutions with European Processors and Accelerate Europe's Adoption of Exascale Supercomputers
- The role of RISC-V in the European Processor Initiative - Interview with Roger Espasa
- RISC-V Turns 15 With Fast Global Adoption
Latest News
- SEMI Reports Worldwide Silicon Wafer Shipments Increase 13% Year-on-Year in Q1 2026
- POLYN Technology Announces Tapeout of Automotive Chip
- QuickLogic Establishes New Banking Relationship and Secures $10 Million Revolving Credit Facility
- TES is extending its PMU IP portfolio for X-FAB’s XT018 - 0.18µm BCD-on-SOI technology.
- RF Front-End Modules & Components IP Trends – Q1 2026 Monitoring Release