Momentum Builds on RISC-V European Adoption
EU funding model needs more industrial focus.
By Pablo Valerio, EETimes | June 9, 2025
Paris – As the RISC-V Europe Summit convened in Paris, the open standard instruction set architecture (ISA) continued its march towards mainstream adoption, sparking discussions among European experts about the continent’s role, its unique strengths, and persistent challenges.
In an exclusive interview for EETimes, Teresa Cervero of the Barcelona Supercomputing Center and Stefan Wallentowitz from Munich University of Applied Sciences, members of the RISC-V Summit Europe steering committee, offered their perspectives from the heart of European academia and research, areas instrumental in fostering the early growth of RISC-V.
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