There's More to The RISC-V China Story
By Junko Yoshida, EEtimes
November 22, 2018
A professor in Beijing corrected us that the China Open Instruction Ecosystem (RISC-V) Alliance, known as CRVA, is no splinter group. We stand corrected. But the fact remains that RISC-V activities in China are fragmented.
Being a reporter is like being the guy who’s trying to bail out the ocean. I know that there is always more to the story than the copy I just filed. My recent blog about RISC-V activities in China is typical.
As soon as my piece, entitled “Why RISC-V Lags in China,” posted on EE Times’ website, I got blowback from Yungang Bao, a professor at the Institute of Computing Technology, Chinese Academy of Sciences in Beijing.
He requested that I set the record straight on three points.
To read the full article, click here
Related Semiconductor IP
- RISC-V Debug & Trace IP
- RISC-V IOPMP IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- 64-bit RISC-V core with in-order single issue pipeline. Tiny Linux-capable processor for IoT applications.
- Multi-core capable RISC-V processor with vector extensions
Related News
- RISC-V Solidifies Presence in China as Global Momentum Builds
- China Unyielding Ascent in RISC-V
- RISC-V Exceeding Expectations in AI, China Deployment
- Script for the Intel foundry story is unwritten
Latest News
- Arteris Deployed by Speedata for Data Center Compute
- Siemens to acquire Defacto Technologies to complement its EDA portfolio with automated SoC design creation
- Mach42 Completes £7M Funding Round, Led by IP Group With Investment From BGF and Foresight Group
- ELECTRA IC Unveils Comprehensive IP Core Suite for Next-Generation Post-Quantum Cryptography
- CAST Enhances Serial Memory Controller IP with Encryption, Low-Power, and ASIL-Ready Options