PACT announced beta availability of its XPP Vectorizing C-Compiler (XPP-VC) technology
C way to reconfigurable ASICs
By David Larner, Embedded Systems
October 4, 2001 (10:51 a.m. EST)
URL: http://www.eetimes.com/story/OEG20011004S0034
PACT announced beta availability of its XPP Vectorizing C-Compiler (XPP-VC) technology. This is designed to allow developers to create "virtual reconfigurable ASICs" using existing C language source code as opposed to hardware programming in Verilog/VHDL or proprietary tools.
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related News
- Axys models new ARM core, Pact speeds up XPP
- PACT XPP Technologies teams with Accent to offer SOC Design Services and Application Platforms for XPP-Based Solutions
- QuickLogic and PACT team to develop Multi-Processor programmable SoC solutions for wireless and multimedia applications
- PACT announces the Smart Media XPP Package for Multi-Standard Video Codecs
Latest News
- First Benchmarks Revealed for Jalapeño, OpenAI’s Clean-Sheet General Purpose AI Accelerator ASIC
- MIPS Leads Open Standards Development for Physical AI Platforms as RISC-V International Premier Member
- SEALSQ’s Subsidiary IC'Alps Advances QASIC Roadmap for Sovereign, Quantum-Resistant Application-Specific Integrated Circuits
- NVMe 2.4 Update Adds Post-Quantum Security, Power Controls
- Agentrys Raises $24.5 Million to Build Agentic Design Automation for Chipmakers