Processing Neuromorphic AI with INTERA’s EAGLE Cognit Accelerator

A full-stack AI ecosystem for Spiking Neural Network (SNN) workloads

BARCELONA -- October 27, 2026 -- INTERA’s EAGLE Cognit accelerator provides configurable vector and matrix computation through a digital SRAM-based near-memory architecture for embedded AI, including support for Spiking Neural Networks (SNNs).

Its software ecosystem aims to bridge the gap between model experimentation and hardware deployment. SNN models represented in the Neuromorphic Intermediate Representation (NIR) can be translated through INTERA’s SNN-MLIR compiler into lower-level MLIR, compiled code, and a self-contained C runtime for execution on embedded targets, including compatible RISC-V systems.

This approach brings together hardware acceleration for sparse neural computation, reproducible training workflows, and compilation tools designed to make embedded SNN deployment more practical.

Why Sparse Activity Matters at the Edge

TinyML enables compact AI models to run on devices with limited memory, power, and processing capacity. Local inference can reduce communication overhead and latency while supporting offline functionality.

Spiking Neural Networks encode information as events over time. When neural activity is sparse, hardware can skip zero-valued inputs and avoid unnecessary computation.

EAGLE's sparse processing engine scans input vectors and skips zero-valued elements. With compatible integer representations, it can accelerate weighted accumulation by processing only active inputs.

The resulting efficiency depends on several factors, including spike representation, activity levels, execution strategies, and the number of timesteps required to reach a decision.

INTERA’s SNN toolkit helps developers optimise models to make effective use of the accelerator.

EAGLE: The Arithmetic Foundation

EAGLE accelerates dot products and matrix-vector multiplication, while matrix-matrix operations are handled in software.

Its architecture combines configurable SRAM banks with SIMD multiply-accumulate units, local accumulators, and a vector cache. By performing arithmetic operations close to stored data, EAGLE reduces unnecessary data movement.

Supported data types: Signed 8-, 16-, and 32-bit integer inputs, with 32-bit signed accumulation. Reduced precision increases arithmetic parallelism, while INTERA's development tools support accuracy verification after quantisation.

In the hardware-software partition described here, neuron dynamics, including membrane updates, leakage, thresholding, reset, and temporal scheduling, are handled by the CPU or other processing components.

This division allows suitable arithmetic operations to benefit from specialised acceleration while other functions remain under software control.

Reproducible Training and Hardware-Aware Compilation

Isolated notebook experiments can make AI models difficult to compare, validate, and reproduce.

INTERA's shared development platform addresses these challenges by integrating tools for experiment management and reproducible workflows:

• UV: Reproducible Python environments and dependency management.
• Hydra: Configuration management and hyperparameter optimisation.
• Pydantic: Strict configuration validation.
• MLflow: Tracking of parameters, performance metrics, and model checkpoints.

For EAGLE-targeted SNNs, evaluation goes beyond conventional accuracy measurements.

Additional metrics include input activity, timesteps per decision, weight precision, and neuron-state memory requirements.

These measurements help developers evaluate the computational and memory requirements of neuromorphic models before deployment.

Key Improvements in the Compilation Workflow

Built on MLIR, the compiler infrastructure bridges high-level neural-network representations and embedded execution.

An SNN-specific dialect captures neuromorphic operations and supports their transformation into lower-level representations.

INTERA's accelerator-specific compilation approach is designed to identify compatible computational kernels, organise model weights, and optimise data placement in EAGLE-accessible memory.

Operations that cannot be accelerated can remain on the CPU, enabling a hardware-software partition adapted to the target architecture.

The publicly available SNN-MLIR implementation also provides a reference CPU compilation path, supporting model validation and portable execution.

Memory and Execution Considerations

Memory behaviour is an important part of EAGLE's execution model.

Because the CPU retains priority over EAGLE-backed memory, concurrent host activity can affect inference throughput.

Data layout, memory alignment, and configuration overhead must therefore be considered carefully, particularly when small computational kernels are executed repeatedly across multiple SNN timesteps.

These considerations are essential for optimising system-level performance.

From Model to Embedded Execution

INTERA addresses three key challenges in bringing neuromorphic AI into embedded products:

1. Reproducible experimentation: Establishing reliable workflows for model development, comparison, and selection.
2. Hardware-aware compilation: Using MLIR-based tools to map compatible operations onto the target hardware.
3. Efficient near-memory processing: Leveraging EAGLE's configurable architecture to accelerate dense and sparse workloads.

Together, these capabilities provide a framework for evaluating and deploying neuromorphic AI in resource-constrained environments.

Explore Intera IP:

• AI accelerator

Explore EAGLE Cognit

EAGLE Cognit is available for integration and evaluation.

Interested in exploring a TinyML or neuromorphic application?

Contact INTERA to discuss your target application, representative datasets, model requirements, and intended hardware platform.

Get in touch: sales@intera-group.com

Contact INTERA Group

Technical References

• INTERA SNN-MLIR Project on GitHub
• SNN-MLIR: An MLIR Dialect for Compiling Neuromorphic SNNs from NIR to Bare-Metal C