Comsis introduce the MimoKit-MAX FPGA platform
Paris, France -- June 30, 2008 -- Comsis introduces the MimoKit-MAX platform. The MimoKit-MAX development kit, based on two high-end field-programmable gate arrays (FPGAs), allows the implementation of extremely complex digital processing blocks such as those found in modern multi-antenna Wlan interfaces. The kit has a sufficient gate capacity to host a complete system-on-programmable chip (SoPC), including microcontroller cores and advanced communication peripherals. The MimoKit-MAX is the ideal platform for Wlan-capable SoC prototyping and incorporates a MIMO RF and analog front-end incorporating 2 major sub-blocks:
The analog block consists of 3 IQ codecs which perform the conversions between the digital and analog domains. Each IQ codec contains two matched 80 Msps 10-bit ADCs, and two matched 80 Msps 10-bit DACs. The digital side of the codec’s bank is connected to an FPGA, while the analog side carries the differential signals to the radio transceivers.
The radio block consists of three 2.4GHz/5GHz dual-band radio transceivers. As the MIMO operation requires the same frequency for all the transceivers, they share a local oscillator reference.
Feature set:
- Two Altera Stratix II devices cumulating more than 3 million ASIC gates equivalent
- 500 FPGA-FPGA connections, including 64 LVDS pairs
- 32 Mbits Flash for code or data storage
- 512 Mbits SDRAM
- Two Gigabit Ethernet PHY transceivers
- PCI interface
- Two USB2 High-speed transceivers, one host and one device
- Two RS232 level shifters
- Three AD9861 IQ codecs for baseband conversion
- MIMO-compatible RF transceivers for configurations up to 3Tx3R
- Supported by the GRLib/Leon3 IP library from Gaisler Research. This is a comprehensive IP library of a Linux-capable 32-bit embedded processor and peripherals
- Compatible with Altera Quartus II design software
Related Semiconductor IP
- ML-KEM-X Post-Quantum Cryptography Core
- AXI5 to/from AXI4 Bridge
- AXI5-Stream to/from AXI4-Stream Bridges
- APB5 to APB4 bridge
- UALink PHY + Controller
Related News
- InCore Unveils SoC Generator Platform: From Idea to FPGA Validation in Minutes; Demonstrates Silicon Proof of Auto-Generated SoC
- Altera and Arrow Electronics Introduce Easy-to-Use MAX 7000 Quick Start Development Kit
- Altera Qualifies Cyclone, ACEX 1K, and MAX Devices for Extended Temperature Range
- Altera Takes Radical New Direction with MAX II CPLDs
Latest News
- CAST Expands Functional Safety IP Line with ASIL B Ready SENT/SAE J2716 Receiver Core
- SkyeChip Advances Custom Interface IP Engagement with Cerebras for Wafer-Scale AI Platforms
- SEALSQ and GlobalFoundries Partner to Accelerate Post-Quantum Cryptography and Quantum Computing Technologies
- Arteris Announces Collaboration with IC-Link by imec to Accelerate Next-Gen AI and HPC Silicon
- SambaNova Completes First Close of $1B Financing at $11B Valuation