Mentor comms cores take aim at Xilinx FPGA lines

Pierre Bricaud, director of R&D for Mentor's intellectual-property (IP) factory, said Mentor is tailoring a selection of communications cores for Xilinx's Virtex, Virtex-E and Spartan-II families of field-programmable gate arrays.

"Customers in the communications sector are doing more designs in FPGAs," said Babak Hedayati, director of marketing and business development for Xilinx's IP Solutions Division. "More and more there is great demand for IP to fill these large-gate-count FPGAs, but users-especially in the communications space-want the same IP that is available for ASICs and they want cores that fit into methodologies such as design reuse."

The initial releases include T1/E1 framers and deframers for use in wireless basestations, satellite modems, next-generation PBXes and voice gateways as well as Internet core and edge routers and multiservice switches.

Bricaud said the cores have not been hand-optimized at the routing stage for Xilinx's architectures, but the company has developed in-depth FPGA synthesis scripts to get maximum performance out of them.

FPGA synthesis tools vary in accuracy and performance. Bricaud said that in this case the optimized register-transfer level netlist for Xilinx architectures was synthesized using Exemplar Logic's Leonardo Spectrum. The cores, of course, can also be synthesized with other third-party synthesis, but performance may not be the same, said Bricaud.

The cores will be sold and supported by Xilinx as LogicCore products and may be licensed online at the Xilinx IP Center at (www.xilinx.com/ipcenter). The cores will be supported and also licensed by Mentor's Inventra IP Division. Visit (www.mentor.com/inventra) for more information.