LeWiz released RISC-V with OmniXtend clustering technology to open source.
December 13, 2022 -- OmniXtend is an open source architecture for clustering of processors (or servers) to remote storage and memory systems on the network. It allows processors such as RISC-V CPU(s) to execute programs stored remotely on network based storage or memory systems. This allows the processor to treat remotely stored information as if the information (program or data) is stored in its local memory. This extends the storage resource of the processor to what's available on the network -- any type of network whether wired or wireless, essentially limitless. Yet, it still can maintain data coherency across the memory hierarchy, keeping the information consistent across the network so if a piece of information is updated (locally or remotely), the processing system does not use stale data, maintaining correctness.
Did you know that such systems can also be fault tolerant? If a processing node is no longer available, other node(s) in the cluster can be made to pick up and continue the processing as if the failure has not occurred. LeWiz develops technology for space and other high reliability applications where fault tolerant is an important capability. It previously developed radiation tolerant RISC-V CPU, memory control and I/O subsystems enabling a system in space to continue to operate even if encountering failure due to radiation.
Released here: https://github.com/lewiz-support/OmniXtend_RemoteAgent_RISC-V
We've also released IP cores to open source on Github. This open source release furthers LeWiz contribution to the open source community advancing state of the art technologies.
Related Semiconductor IP
- RISC-V Debug & Trace IP
- RISC-V IOPMP IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- 64-bit RISC-V core with in-order single issue pipeline. Tiny Linux-capable processor for IoT applications.
- Multi-core capable RISC-V processor with vector extensions
Related News
- LeWiz Open Source LVDS Transceiver Design
- PUFsecurity IP Open Source Program: Bridging the Gap in Chip Security
- CHIPS Alliance Announces AIB 2.0 Draft Specification to Accelerate Design of Open Source Chiplets
- OpenHW Ecosystem Implements Imperas RISC-V reference models for Coverage Driven Verification of Open Source CORE-V processor IP cores
Latest News
- Year-to-Date Global Semiconductor Sales Top $1 Trillion Through August
- Xiphera launches nQrux® Root of Trust with Post-Quantum Cryptography
- Skyechip Joins Rapidus Core Ecosystem, Bringing Advanced Silicon IP For AI and HPC to Japan's 2nm Platform
- GUC Monthly Sales Report – September 2026
- Rapidus Unveils “Rapidus CORE”, New Global Ecosystem Framework Supporting the Development and Mass Production of Cutting-Edge Semiconductors