JEDEC® Releases Updated LPDDR5/5X SPD Standard with Enhanced Mode‑Switching Support
ARLINGTON, Va.-- March 24, 2026 -- JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced the publication of JESD406-5D: LPDDR5/5X Serial Presence Detect (SPD) Contents standard, an update of the Revision C standard that adds support for calculating recovery time when switching operating modes. JESD406-5D is available for free download from the JEDEC website.
LPDDR5/5X memory devices are capable of supporting two sets of timing parameters: a full speed mode and a reduced speed mode that consumes less power. This feature allows for longer battery life for mobile devices which are a common application for LPDDR5/5X chips and modules and may also be leveraged by data centers as the use of LPDDR5/5X devices grows. The updated JESD406-5 standard documents key parameters for calculating the switching time between fast and low power modes, making the feature more efficient and allowing higher system performance.
“Reducing power consumption has become imperative for computing systems as the use of AI and other demanding applications accelerate,” said Bill Gervasi, Chair of the JEDEC SPD Task Group. “The updates to the JESD406-5 standard are an important enabler for systems to optimize performance while maintaining a lower power profile.”
Explore LPDDR5 IP
About JEDEC
JEDEC is the global leader in the development of standards for the microelectronics industry. Thousands of volunteers representing over 380 member companies work together in more than 100 JEDEC committees and task groups to meet the needs of every segment of the industry, for manufacturers and consumers alike. The publications and standards generated by JEDEC committees are accepted throughout the world. All JEDEC standards are available for download from the JEDEC website. For more information, visit https://www.jedec.org.
Related Semiconductor IP
- LPDDR5 Controller - Validates memory controllers for high-speed, power-efficient performance
- Simulation VIP for LPDDR5
- LPDDR5 IP solution
- LPDDR5 Synthesizable Transactor
- LPDDR5 DFI Synthesizable Transactor
Related News
- JEDEC Releases New Standard for LPDDR5/5X Serial Presence Detect (SPD) Contents
- JEDEC Announces Annual Update of DDR5 Serial Presence Detect (SPD) Contents Standard
- JEDEC Updates Standard for Low Power Memory Devices: LPDDR5
- JEDEC Publishes Update to LPDDR5 Standard for Low Power Memory Devices
Latest News
- POLYN Technology Announces Tapeout of Automotive Chip
- QuickLogic Establishes New Banking Relationship and Secures $10 Million Revolving Credit Facility
- TES is extending its PMU IP portfolio for X-FAB’s XT018 - 0.18µm BCD-on-SOI technology.
- RF Front-End Modules & Components IP Trends – Q1 2026 Monitoring Release
- IC Manage Advances GDP-AI for Custom IC Design with Virtuoso