Vendor: SmartDV Technologies Category: Protocol Bridge

LPDDR5 DFI Synthesizable Transactor

LPDDR5 DFI Synthesizable Transactor provides a smart way to verify the LPDDR5 DFI component of a SOC or a ASIC in Emulator or FPG…

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Overview

LPDDR5 DFI Synthesizable Transactor provides a smart way to verify the LPDDR5 DFI component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's LPDDR5 DFI Synthesizable Transactor is fully compliant with standard DFI 5.0 Specification and provides the following features.

Key features

  • Compliant with DFI version 5.0 Specifications.
  • Supports LPDDR5 devices compliant with JEDEC LPDDR5 SDRAM Standard JESD209-5.pdf, JESD209-5A and LPDDR5X (Draft).
  • Supports for Read data bus inversion.
  • Supports for Write data bus inversion.
  • Supports for DFI disconnect during training.
  • Supports for WCK Control interface.
  • Supports write clock free running mode.
  • Supports data copy low power function and write x operation.
  • Supports for 2:1 and 4:1 CKR mode.
  • Supports all data rates as per specification.
  • Supports write data mask operation.
  • Supports WCK2CK Sync operation.
  • Supports deep sleep mode.
  • Supports power down mode and self-refresh operation.
  • Supports frequency set point operation.
  • Supports programmable clock frequency of operation.
  • Supports following training modes.
    • Command bus training
    • WCK2CK leveling
    • WCK-DQ training
    • Enhanced RDQS training mode
  • Supports DRAM Clock disabling feature.
  • Supports Error signaling
  • Supports all types of timing and protocol violation detection
  • Checks for following:
  • Check-points include power on, initialization and power off rules
    • State based rules, active command rules
    • Read/Write command rules etc
    • All timing violations

Block Diagram

LPDDR5 DFI Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the LPDDR5 DFI testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and function's used in verification env
  • Documentation contains User's Guide and Release notes

Specifications

Identity

Part Number
LPDDR5 DFI Transactor
Vendor
SmartDV Technologies
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact SmartDV Technologies

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Frequently asked questions about Protocol Bridge IP cores

What is LPDDR5 DFI Synthesizable Transactor?

LPDDR5 DFI Synthesizable Transactor is a Protocol Bridge IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this Protocol Bridge?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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