IP Integration Challenges Rising

Need for more support from IP providers grows with complexity.

Ann Steffora Mutschler, Semiconductor Engineering
July 24, 2014

It’s not just lithography that is putting a crimp in sub-28nm designs. As more functions, features, transistors and software are added onto chips, the pressure to get chips out the door has forced chipmakers to lean more heavily on third-party IP providers.

Results, as you might expect, have been mixed. The number of blocks has mushroomed, creating its own web of complexity. So while IP can and does speed up the design process, managing the complexity of the IP itself and the interactions between growing numbers of IP blocks is a challenge by itself—something that is complicated further by IP reuse and a mix of externally developed and internally developed IP in an effort to amortize costs and improve ROI.

“Typically there are 200 to 300 IP blocks and a large number of SRAMs,” said Hem Hingarth, vice president of engineering at Synapse Design. “IP has to meet requirements for software drivers, RTL design, verification and physical design views.”