Intel Reports Tepid Progress on 10 nm
By Dylan McGrath, EETimes
October 26, 2018
SAN FRANCISCO — Intel said that it’s making progress on improving 10-nm yields and reiterated its pledge to have 10-nm chips shipping by the 2019 holiday season.
In a conference call with analysts following a financial report that beat analysts’ expectations for the 12th straight quarter, Venkata (Murthy) Renduchintala, president of Intel’s Technology, Systems Architecture and Client Group, said that 10-nm yields are now tracking roughly in line with what the company experienced at the 14-nm node when it prepared to make that transition.
“We’re still very much reinforcing and reaffirming our previous guidance that we believe that we’ll have 10 nm shipping by holiday of 2019,” said Renduchintala. “And if anything, I feel more confident about that at this call than I did on the call a quarter ago. So we’re making good progress, and I think we’re making the quarter-on-quarter progress that’s consistent with prior generations having reset the progress curve.”
To read the full article, click here
Related Semiconductor IP
- 1.6T Ultra Ethernet Controller
- Chiplet Die-to-Die Interconnect IP Solution
- High speed MACsec Engine 100G/200G/400G/800G/1.6T
- Temperature/Voltage sensors
- AMBA Bus Host to eSPI Controller/Target
Related News
- Intel: 450-mm wafers must wait on 10-nm
- Quad patterning a possibility at 10nm, says TSMC
- UMC joins IBM chip alliance for 10nm process development
- Common Platform in Preparation for SOI, FinFETs at 10nm
Latest News
- Imec unlocks fourfold UWB range extension using world-first narrowband receiver chip compliant with IEEE 802.15.4ab standard
- Alliance for Open Media Releases AV2 Codec, Advancing Next-Generation Open Video Coding
- VeriSilicon Drives Commercial Adoption of AV2 Across Next-Generation Video and Streaming Applications
- Cadence Announces Collaboration with Intel Foundry to Accelerate Intel 14A Process Optimization for HPC and Mobile Designs
- Menta and Presto Engineering Announce Strategic Collaboration to Accelerate Adaptive ASIC Architectures with Embedded FPGA Technology