Common Platform in Preparation for SOI, FinFETs at 10nm
Peter Clarke, Electronics360
08 April 2014
A team of engineers from IBM Microelectronics, Globalfoundries, Samsung, STMicroelectronics and UMC are due to present a 10nm logic platform that supports FinFETs on both bulk CMOS and on silicon-on-insulator wafers.
The presentation of paper 2.2 is set to be one of the highlights of the Symposium on VLSI Technology due to take place June 9 to 12 at Honolulu, Hawaii. It represents a coming together of the interests of the FinFET and fully-depleted silicon-on-insulator (FDSOI) camps, but not yet a complete merging.
To read the full article, click here
Related Semiconductor IP
- DSP-Based 112G SerDes
- XTAL oscillator in TSMC-7nm
- GPU
- V-by-One Verification IP
- AI model compression IP
Related News
- Synopsys' Custom Compiler Certified for TSMC 10-nm and 7-nm FinFET Process Nodes
- Silicon Creations Taps Silvaco's Custom Design Flow for 10nm FinFET Designs
- eMemory's NeoFuse IP Verified in TSMC 10nm FinFET Process
- Samsung Electronics on Track for 10nm FinFET Process Technology Production Ramp-up
Latest News
- Arteris Deployed by Speedata for Data Center Compute
- Siemens to acquire Defacto Technologies to complement its EDA portfolio with automated SoC design creation
- Mach42 Completes £7M Funding Round, Led by IP Group With Investment From BGF and Foresight Group
- ELECTRA IC Unveils Comprehensive IP Core Suite for Next-Generation Post-Quantum Cryptography
- CAST Enhances Serial Memory Controller IP with Encryption, Low-Power, and ASIL-Ready Options