IBM adds TCP/IP coprocessor to PowerPC

IBM adds TCP/IP coprocessor to PowerPC
By Anthony Cataldo, EE Times
May 2, 2002 (2:54 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020502S0027

SAN JOSE, Calif. — IBM Corp. has tailored its PowerPC architecture for packet processing by adding a TCP/IP coprocessor to its latest 440GX device.

Designed to take most of the strain off the CPU during packet processing, the TCP/IP assist engine handles checksum generation logic for packet headers and data in transmit, provides checksum verification logic in the receive path and supports TCP segmentation in transmit.

The hardware-assist mechanism works with Ethernet II formatted frames, IEEE-formatted frames and IEEE 802.3ac frames. By adding this coprocessor, the CPU bandwidth required for these packet processing tasks can be reduced as much as two-thirds, according to IBM.

The 440GX processor itself is based on a PowerPC 440 core and features a dual-issue superscalar seven-stage pipeline. The 32-bit design has a worst-case performance of 500-MHz, said PowerPC advanced technology engineer Joyce Fitz Ruff.

Conn ected to the processor local bus are a DDR SDRAM controller, a PCI-X interface core, an Ethernet interface, an I20 messaging unit and 256 kbytes of SRAM. The processor local bus can run at 166 MHz and transfer data at 5.3 gigabytes/second.

IBM expects to deliver samples of the 440GX by the fourth quarter, Fitz Ruff said.

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