From Shrinking Transistors to Compressing Time: Deciphering Huawei’s τ Law
Huawei’s answer to Moore’s Law without EUV promises 14A performance by 2031.
By Echo Zhao, EE Times | May 26, 2026

As Moore’s Law gradually becomes ineffective, the semiconductor industry seeks new paths to performance growth. At the 2026 IEEE ISCAS conference in Shanghai, Huawei said it has shifted performance optimization from “geometric size” to “time compression,” and validated this through engineering practice (using 381 chips designed and mass-produced over the past six years).
In her keynote speech at ISCAS 2026, He Tingbo, president of Huawei Semiconductor, began by saying, “Over the past six years, I’ve often been asked: How did you survive and return to the forefront in highly competitive industries such as smartphones and AI?”
To read the full article, click here
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related News
- Necessity is the Mother of Invention: Huawei Replaces Moore’s Law With Her’s Law
- Huawei Files Lawsuit Against Motorola for IP Infringement
- TSMC Defends Transistor Scaling Amid Huawei’s ‘Her’s Law’ Proposal
- Nokia, Huawei sign W-CDMA patent licensing deal
Latest News
- First Benchmarks Revealed for Jalapeño, OpenAI’s Clean-Sheet General Purpose AI Accelerator ASIC
- MIPS Leads Open Standards Development for Physical AI Platforms as RISC-V International Premier Member
- SEALSQ’s Subsidiary IC'Alps Advances QASIC Roadmap for Sovereign, Quantum-Resistant Application-Specific Integrated Circuits
- NVMe 2.4 Update Adds Post-Quantum Security, Power Controls
- Agentrys Raises $24.5 Million to Build Agentic Design Automation for Chipmakers