TSMC Defends Transistor Scaling Amid Huawei’s ‘Her’s Law’ Proposal
By Sally Ward-Foxton, EE Times | June 1, 2026
AMSTERDAM, The Netherlands — At TSMC’s European Symposium, Kevin Zhang, senior VP and deputy co-chief operating officer at market-leading foundry TSMC, responded to questions from reporters about Huawei’s proposal to stop measuring industry progress on transistor density.
Huawei proposed Her’s Law, analogous to Moore’s Law, based on Tao scaling, a method of measuring industry progress in terms of overall speedup rather than purely on transistor density. Huawei does not have access to EUV machines necessary to shrink transistor geometries beyond 7-nm process nodes.
Asked about Huawei’s Tao scaling theory, Zhang said that while he had not looked into it in detail, Tao scaling appears to be a matter of 3D integration, which can bring different functions closer together to reduce delays between chips.
To read the full article, click here
Related Semiconductor IP
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
- 3.3V Capable GPIO on TSMC 28nm RF HPC+
- 1.2V Thin Oxide GPIO on TSMC 28nm RF HPC+
- LDO Voltage Regulator, 250 mA, TSMC N3P
- LDO Voltage Regulator, Adjustable 0.45 V to 0.9 V Output, 30 mA, TSMC N3P
Related News
- Necessity is the Mother of Invention: Huawei Replaces Moore’s Law With Her’s Law
- From Shrinking Transistors to Compressing Time: Deciphering Huawei’s τ Law
- Transistor Count Trends Continue to Track with Moore's Law
- The Semiwise's Flat Field Transistor enables the continuation of DRAM scaling
Latest News
- Arteris Deployed by Speedata for Data Center Compute
- Siemens to acquire Defacto Technologies to complement its EDA portfolio with automated SoC design creation
- Mach42 Completes £7M Funding Round, Led by IP Group With Investment From BGF and Foresight Group
- ELECTRA IC Unveils Comprehensive IP Core Suite for Next-Generation Post-Quantum Cryptography
- CAST Enhances Serial Memory Controller IP with Encryption, Low-Power, and ASIL-Ready Options