TSMC Defends Transistor Scaling Amid Huawei’s ‘Her’s Law’ Proposal
By Sally Ward-Foxton, EE Times | June 1, 2026

AMSTERDAM, The Netherlands — At TSMC’s European Symposium, Kevin Zhang, senior VP and deputy co-chief operating officer at market-leading foundry TSMC, responded to questions from reporters about Huawei’s proposal to stop measuring industry progress on transistor density.
Huawei proposed Her’s Law, analogous to Moore’s Law, based on Tao scaling, a method of measuring industry progress in terms of overall speedup rather than purely on transistor density. Huawei does not have access to EUV machines necessary to shrink transistor geometries beyond 7-nm process nodes.
Asked about Huawei’s Tao scaling theory, Zhang said that while he had not looked into it in detail, Tao scaling appears to be a matter of 3D integration, which can bring different functions closer together to reduce delays between chips.
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