Dolphin Integration launches their SESAME library for High Voltage and Low Leakage in 0.18 µm
- Direct connection to the battery (e.g. Li-Ion) for some logic islets of SoCs requires dealing with “high voltage”, up to 3.6 V, while for others ultra low leakage is needed far below the performances offered by products available on the market.
SESAME uHVuLL is the solution to these needs as it enables a leakage reduction by a ratio of 1000, while offering the capability to operate between 1.6 V to 3.6 V!
For more information on this state-of-the-art product, click here.
A free “Evaluation Tutorial” is provided with each evaluation kit for a smooth and fast discovery.
About Dolphin Integration’s SESAME library
SESAME is a grouping of specialized and well-structured “library stems”: each of them library is ultimately optimized for one prime criterion, namely Low Power Consumption (LC), High Density (HD), Low Leakage (LL), while simultaneously offering a good performance on a second criterion.
SESAME is classified as a “Reduced Cell Stem Library” (RCSL): each library stem results from a handcrafted design, with a unique advantage. Indeed, each cell is carefully optimized at both electrical and layout levels not only to provide the highest performance on the chosen optimization criterion of the stem, but also to enable the composition of stems, for an optimization with constraint, e.g. high density but with tight timing constraints.
More information on SESAME at: http://www.dolphin.fr/sesame
Related Semiconductor IP
- ONFI/Toggle IP
- 8 - 24MHz Xtal Oscillator on TSMC 22nm
- 32kHz Xtal Oscillator on TSMC 22nm
- 1.056GHz SSCG PLL on TSMC 40nm
- 1.25GHz Multiplying PLL on TSMC 40nm
Related News
- Lattice FPGAs with High I/O Density Bring Low Power Signal Bridging and Interface Management to Edge Devices
- sureCore Unveils New Low Voltage Register Files
- USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP Cores for High Bandwidth, Low Power data communication in PCs, Mobiles, SSDs, and other Multimedia Devices.
- Augment your Peripheral slot's performance with the Low Power and High Throughput PCIe 4.0 PHY IP Cores in 12FFC with matching PCIe 4.0 Controller IP Cores
Latest News
- OpenTitan project kicks off the Peppermint integrated root-of-trust for area-constrained SoCs
- SiFive Paves the Path to Accelerated Adoption of RISC-V in the Datacenter with the BigSky Development Server
- Perceptia Releases Design Kit for pPLL03 on Samsung Foundry 14LPU Platform
- Brite Semiconductor Releases 28nm High-Performance SAR ADC IP, Driving Upgrades for High-Speed Signal Chain Applications
- Synopsys Updates CXL IP Portfolio for AI-Era Infrastructure