Firm licenses noise sign-off tool
Firm licenses noise sign-off tool
By Michael Santarini, EE Times
September 11, 2000 (9:44 a.m. EST)
URL: http://www.eetimes.com/story/OEG20000907S0047
SAN MATEO, Calif. CadMOS Design Technology Inc. has announced it has licensed use of its CeltIC crosstalk analyzer to Cirrus Logic Inc. for 0.18-micron coupling noise sign-off. "Coupling noise is a critical issue in ultradeep-submicron design," said H. Ravindra, vice president of Advanced Technology and Business Development at Cirrus Logic. "At 0.18 micron we will have to perform coupling noise analysis before we can sign off the design." Jim McCanny, vice president of business development at CadMOS, said Cirrus designers plan to use the tool to tell them if a given design has a functional failure or if it has a noise glitch. "Noise can cause nets to fail or they can change the voltage level on a net so that the net turns from a zero to one or a one to zero," said McCanny. McCanny said Cirrus' designers will also use CeltIC to account for delays caused by noise. "Their engineers can generate an SDF [Standard Delay Format] file with CeltIC and run that in a static timing tool to see the impact of noise on delay." McCanny said the company has four other CeltIC customers, including Texas Instruments. A perpetual license for CeltIC starts at $75,000. Time-based licenses start at $36,250 per year.
Related Semiconductor IP
- GPU
- V-by-One Verification IP
- AI model compression IP
- Hardware compressed memory IP for CXL devices and chip-to-chip links
- Hardware link (de)compression IP for die-to-die, chip-to-chip, and DRAM interfaces
Related News
- SkyWater Establishes Cryogenic Lab, Utilizes FormFactor's Leading Tool for RTS Noise Detection in Read-Out Integrated Circuit Applications
- Firm does marketing, sales and legal for IP vendors
- Altera kicks off mask-programmable PLD program
- LSI Logic licenses packaging technology to Taiwan firm
Latest News
- TSMC Boosts 2026 Expansion Budget, Adds $100B to U.S. Investment
- ZeroPoint Technologies Announces ZeroStream
- TSMC Reports Second Quarter EPS of NT$27.25
- Rapidus and Cadence Partner on Agentic AI for Advanced SoC Design
- Defacto’s SoC Compiler Drastically Improved Productivity of L&T Semiconductor Technologies