Video: Where hardware and software collide
Dylan McGrath, EE Times
(04/03/2009 8:55 PM EDT)
SAN JOSE, Calif.—Chipmakers are taking on responsibility for the development of more embedded software, resulting in a clash of cultures between hardware designers and software developers and necessitating a more system-level approach to design, according to executives on a panel discussion at ESC Silicon Valley this week.
Chris Rowen, chief technology officer at chip and IP vendor Tensilica Inc., said his company tackles this clashing of cultures by work with both sides to understand what pressures they are under—reliability and flexibility on the hardware side, and power efficiency and cost on the software side.
Ultimately, Rowen said, program managers and system designers or whoever is responsible for the combination hardware and software deliverable is the "ultimate arbitrator in how you bring these two together." Rowen added that the emergence of multicore architecture has contributed to the blurring of hardware and software design.
(04/03/2009 8:55 PM EDT)
SAN JOSE, Calif.—Chipmakers are taking on responsibility for the development of more embedded software, resulting in a clash of cultures between hardware designers and software developers and necessitating a more system-level approach to design, according to executives on a panel discussion at ESC Silicon Valley this week.
Chris Rowen, chief technology officer at chip and IP vendor Tensilica Inc., said his company tackles this clashing of cultures by work with both sides to understand what pressures they are under—reliability and flexibility on the hardware side, and power efficiency and cost on the software side.
Ultimately, Rowen said, program managers and system designers or whoever is responsible for the combination hardware and software deliverable is the "ultimate arbitrator in how you bring these two together." Rowen added that the emergence of multicore architecture has contributed to the blurring of hardware and software design.
To read the full article, click here
Related Semiconductor IP
- NPU IP
- JPEG XL Encoder
- I2C Master/Slave Controller Core
- NVMe Validation Test Suite
- Hybrid Memory Cube Verification IP
Related News
- CoWare to Showcase its ESL Design Solutions at Upcoming Design Automation Conference, June 7-11 in San Diego
- Sonics integrates SMART Interconnect IP with Cadence and Coware Electronic System-Level (ESL) design-for-verification flow
- ESL startup tools for processor-based design
- ESL tools: Are EDA giants in the game?
Latest News
- intoPIX to Demonstrate JPEG XS, IPMX and SMPTE ST 2110 Solutions at NAB Show New York 2026
- GF unveils roadmap to deliver the world’s most advanced FD-SOI platform for Physical AI
- GlobalFoundries marks Dresden expansion milestone, announces next-generation platform for Physical AI
- TSMC September 2026 Revenue Report
- Lattice Collaborates with Arm to Advance Secure, Adaptable AI Data Center Infrastructure