Dolphin Integration reveals advanced low-power solutions at the TSMC 2015 OIP Forum
Grenoble, France – September 7, 2015 - Dolphin Integration announces its participation to the TSMC Open Innovation Platform (OIP) Forum at the Santa Clara Convention Center, CA.
During the event Gilles Depeyrot, CEO of Dolphin Integration, will present a breakthrough low-power design methodology associated with a set of standardized Virtual Components of Silicon IP enabling to optimize low power networks in a SoC as well as associated modeling and simulation solutions.
« Our objective is to provide standardized building blocks for power, control and clock networks to simplify SoC integration by our customers while optimizing the overall power consumption. » stated Gilles Depeyrot.
As reducing power consumption is a real challenge, the presentation will deal with How to avoid blindness about power consumption during low-power SoC design?
- Selection of specific IPs for the always-on domain
- Implementation and control of power domains
- Optimization of a low power SoC during software development
- Construction of noise resilient subsystems
Attendees are also welcome to visit Dolphin Integration’s booth #312 in order to go further and discover the Silicon IP product portfolio.
For further information feel free to visit our website at www.dolphin-ip.com.
Want to book a meeting with one of our sales representative during TSMC 2015 OIP forum? Please contact us at lucile.denardo@dolphin.fr
About Dolphin Integration
Dolphin Integration contributes to "enabling mixed signal Systems-on-Chip" for worldwide customers - up to the major actors of the semiconductor industry - with Silicon IP components best at low-power consumption.
This wide offering is based on innovative libraries of standard cells, register files, memory generators and power regulators. Complete networks for power supply can be flexibly assembled together with their loads: from high-resolution converters for audio and measurement applications to power-optimized micro-controllers of 8 or 16 and 32 bits.
Over 30 years of diverse experiences in the integration of silicon IP components and providing services for ASIC/SoC design and fabrication, with its own EDA solutions solving unaddressed challenges, make Dolphin Integration a genuine one-stop shop covering all customers’ needs for specific requests.
The company striving to incessantly innovate for its customers’ success has led to two strong differentiators:
- state-of-the-art “configured subsystems” for high-performance applications securing the most competitive SoC architectural solutions,
- a team of Integration and Application Engineers supporting each user’s need for optimal application schematics, demonstrated through EDA solutions enabling early performance assessments
Its social responsibility has been from the start focused on the design of integrated circuits with low-power consumption, placing the company in the best position to now contribute to new applications for general power savings through the emergence of the Internet of Things.
Related Semiconductor IP
- JPEG XL Encoder
- I2C Master/Slave Controller Core
- NVMe Validation Test Suite
- Hybrid Memory Cube Verification IP
- nQrux® Root of Trust IP
Related News
- Cadence to Demonstrate 10nm FinFET Design Solutions at TSMC 2015 OIP Ecosystem Forum
- 2025 TSMC OIP Ecosystem Forum Highlights Aion Silicon’s Leadership in Advanced SoC Design
- Analog Bits Adds New Power and Energy Management IP Blocks Proven on TSMC N2P and N3P Processes at TSMC 2025 OIP Ecosystem Forum
- Innosilicon to Showcase High-Speed Interface IP and Advanced SoC Solutions at the 2025 TSMC OIP Ecosystem Forum
Latest News
- TSMC September 2026 Revenue Report
- Lattice Collaborates with Arm to Advance Secure, Adaptable AI Data Center Infrastructure
- ZLG Selects CAST CAN XL and TSN IP for Next-Generation Vehicle-Network Development and Test Tools
- Vayavya Labs and Tenstorrent Partner to Accelerate RISC-V Hardware and Software Development Through Virtual Platform Modeling
- RaiderChip’s Edge NPU reaches more than 50 Generative AI Models with the addition of Qwen3.8-27B