CynApps and Chronology Partner to Reduce Design Verification Time

SANTA CLARA, Calif.----June 19, 2000--Chronology Corporation and CynApps today announced Chronology's plans to deliver support for CynApps' Cynlib class library. Design and verification teams will be able to use Chronology's QuickBench Verification Suite to automate the generation of complete functional testbenches in a Cynlib C++ environment.

The latest version of the CynApps open-source class library and simulator that enables hardware modeling in C/C++, Cynlib 1.2, is now compatible with a variety of EDA tools from leading vendors. New features include support for VSIA data types, tri-state signals for modeling buses, and Cynlib API to simplify the integration of the Cynlib simulator into existing tools.

Chronology's QuickBench Verification Suite enables designers and verification engineers to develop and reuse complex testbenches for verifying their designs. It is a structured, transaction-based solution providing a unified verification flow for block- and chip-level design. It consists of modular products -- QuickBench Modeler, QuickBench Sequencer, and QuickDrive -- available as an integrated solution for complete testbench generation or separately to integrate with existing capabilities.

``We are happy to have Chronology join the Cynlib community,'' said Dr. John Sanguinetti, president of CynApps. ``Cynlib will naturally be used in the creation of complex designs, creating a real need for sophisticated testbench automation products like QuickBench. We have made an effort to make Cynlib as open as possible so tools like this can be easily integrated into a C++/Cynlib environment. The result is a rich design and verification environment for higher-level design.''

``As designers incorporate the use of a new C++ based design system, they will see value in the availability of a testbench creation environment that supports this new methodology,'' said David Evans, Chronology's president. ``We believe our QuickBench Verification Suite can provide the right level of automation and structure for testbench creation in a Cynlib-based environment.''

About Chronology Corporation

Chronology Corporation is a leading supplier of testbench automation and interface specification solutions. The company offers the QuickBench Verification Suite for complete testbench generation and TimingDesigner for the creation and analysis of timing specifications for design interfaces. Chronology products are sold and supported through a worldwide network of direct sales representatives and independent EDA distributors. Chronology is a privately held company based in Redmond, Washington. For more information about Chronology and its products, call (800) 800-6494 or visit their website at www.chronology.com.

About CynApps

CynApps was founded in 1998, to develop tools to support the use of higher levels of abstraction for hardware design. By enabling C++ to be used as a hardware description language through the development of the Cynlib® class library, CynApps has eliminated the need to manually rewrite an algorithm using a language such as Verilog or VHDL prior to synthesis. Cynlib is available under an open source license.

The company now offers a complete tool-suite that supports successive elaboration of an abstract C/C++ description into a hardware description, to be synthesized automatically. The Cynlib environment is the most complete C++ design environment available today. CynApps has its worldwide headquarters in Santa Clara, Calif. and can be reached at (408) 588-4000, or on the web at www.cynapps.com.

QuickBench, TimingDesigner, and Chronology are registered trademarks and QuickBench Verification Suite, QuickBench Sequencer, QuickBench Modeler, QuickBench Manager, RAVE, QuickDrive, and TimingViewer are trademarks of Chronology Corporation.

     Chronology
     Michael Meredith, 425/869-4227, ext 104
     mmeredith@chronology.com
     or
     lochpr
     Jim Lochmiller, 541/552-0616
     lochpr@yahoo.com