CXL Overcomes Hierarchical Routing Limits
By Gary Hilson, EETimes (January 9, 2024)
The feature updates in CXL 3.1 were already in play when the standard was last updated, but members of the CXL Consortium needed a little more time to make sure they could work across different architectures and further finesse security features that were introduced in 2.0, Kurtis Bowman, the Consortium’s working group co-chair, told EE Times.
Moving to a fabric is not a small task, he added. “That took some time to get worked out.”
With hierarchical-based routing, memory devices at the bottom must go up to the host if they want to communicate with each other, even if they sit right beside each other. Bowman said port-based routing (PBR) in CXL 3.1 allows for much more efficient switching. Reducing the number of hops necessary by staying in the memory domain dramatically reduces latency, he said, and it also enables more complex topologies.
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