Chiplets Get a Formal Standard with UCIe 1.0
Recent uptick in chiplet interest has led to concerns about lack of best practices
The recently announced Universal Chiplet Interconnect Express (UCIe) 1.0 specification covers the die–to–die I/O physical layer, die–to–die protocols, and a software stack model leveraging PCI Express (PCIe) and Compute Express Link (CXL) industry standards.
It’s fair to say that UCIe is a long time coming. Chiplets aren’t new, but recent uptick in interest in the technology has raised concerns about the need for a formal standard and best practices.
UCIe has garnered a lot of interest in recent years because of its tried–and–true nature and its ability to help semiconductor companies solve common problems faced today. Chiplets offer an approach to semiconductor design and integration that hold the promise of speeding things up with Moore’s Law, which is now nearly six decades old. The pace of semiconductor manufacturing advancement has also been waning as of late.
To read the full article, click here
Related Semiconductor IP
- UCIe D2D Adapter
- UCIe D2D Adapter & PHY Integrated IP
- D2D UCIe 1.1
- D2D UCIe 1.0
- 40G UltraLink D2D PHY
Related News
- SmartDV Charts Course Toward Chiplets, Joins Universal Chiplet Interconnect Express (UCIe)
- QuickLogic and YorChip Partner to Develop Low-Power, Low-Cost UCIe FPGA Chiplets
- CHIPLETs From Aurora VLSI Speed SOC Development
- Exostiv Labs now supports Intel Stratix 10 FPGA
Latest News
- Sofics Extends Interface Voltage Options in TSMC FinFET and Nanosheet Technologies
- aiMotive and Cadence Demonstrate Layer-by-Layer Workload Placement Across Independent AI Engines
- Alchip collaborates with Synopsys to Address Scale Up and Out Bandwidth Constraints
- M31 and Ambiq Collaborate on TSMC N12e® Foundation IP to Address Demanding SoC Power and Area Targets
- Siemens and TSMC advance AI-powered semiconductor design automation