Chiplets Get a Formal Standard with UCIe 1.0
Recent uptick in chiplet interest has led to concerns about lack of best practices
By Gary Hilson, EETimes (April 8, 2022)
The recently announced Universal Chiplet Interconnect Express (UCIe) 1.0 specification covers the die–to–die I/O physical layer, die–to–die protocols, and a software stack model leveraging PCI Express (PCIe) and Compute Express Link (CXL) industry standards.
It’s fair to say that UCIe is a long time coming. Chiplets aren’t new, but recent uptick in interest in the technology has raised concerns about the need for a formal standard and best practices.
UCIe has garnered a lot of interest in recent years because of its tried–and–true nature and its ability to help semiconductor companies solve common problems faced today. Chiplets offer an approach to semiconductor design and integration that hold the promise of speeding things up with Moore’s Law, which is now nearly six decades old. The pace of semiconductor manufacturing advancement has also been waning as of late.
To read the full article, click here
Related Semiconductor IP
- UCIe D2D Adapter & PHY Integrated IP
- UCIe D2D Adapter
- D2D UCIe 1.1
- D2D Controller addon for D2D SR112G PHY with CXS interface
- D2D UCIe 1.0
Related News
- SmartDV Charts Course Toward Chiplets, Joins Universal Chiplet Interconnect Express (UCIe)
- QuickLogic and YorChip Partner to Develop Low-Power, Low-Cost UCIe FPGA Chiplets
- CHIPLETs From Aurora VLSI Speed SOC Development
- Stratix 10 FPGA: REFLEX CES is Shipping the Cloud Computing COTS Board "XpressGXS10-FH200G", and the Sargon Stratix 10 GX Development Kit
Latest News
- Alliance for Open Media Releases AV2 Codec, Advancing Next-Generation Open Video Coding
- VeriSilicon Drives Commercial Adoption of AV2 Across Next-Generation Video and Streaming Applications
- Cadence Announces Collaboration with Intel Foundry to Accelerate Intel 14A Process Optimization for HPC and Mobile Designs
- Menta and Presto Engineering Announce Strategic Collaboration to Accelerate Adaptive ASIC Architectures with Embedded FPGA Technology
- MIPI A-PHY To Power Industry’s First Four-Company Automotive SerDes Interoperability Demonstration at AutoSens USA