CEA Backs RISC-V for Sovereign, Scalable Computing

Speaking at the recent RISC-V Summit Europe 2025 in Paris, Thomas Dombek, head of Digital Integrated Circuits and Systems Department at CEA, looked back on seven years of involvement in the RISC-V ecosystem.

By Anne-Françoise Pelé, EETimes Europe | May 28, 2025

It’s been fifteen years since RISC-V turned the page on closed, proprietary ISAs and opened a new chapter in computing. Its open ISA allows the architecture to be adapted to different application domains, from performance to low-energy consumption and from safety to security. Speaking at the recent RISC-V Summit Europe 2025 in Paris, Thomas Dombek, head of Digital Integrated Circuits and Systems Department at CEA, looked back on seven years of involvement in the RISC-V ecosystem.

“Over the years, we have been at the forefront of heterogeneous integration, always with a close link to semiconductor technology, ultra-low power systems, and efficient AI,” Dombek said. “We have used different types of processing systems, but more and more, research goes around RISC-V processors and surrounding systems.” 

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