ASICFPGA releases new advanced Demosaicing core
February 26, 2024 -- ASICFPGA has announced the release of new advanced Demosaicing core, support Multiple Pixel Processing of 1, 2, or 4 pixels per clock. In previous versions of the core, the performance of reducing false color and zipper errors was insufficient. The new advanced demosaicing core can keep high resolution in spite of reducing false color and zipper errors.
Features of new advanced Demosaicing core:
- RGB Bayer image sensor support
- Multiple pixel processing of 1, 2, or 4 pixels per clock
- High quality interpolation
- 8, 10, 12 and 14 bit input and output precision
- Advanced demosaicing algorithm
- Reduced zipper errors
- Reduced false errors
Related Semiconductor IP
- Camera Demosaicing IP (RCCB)
- Camera Interface (AHB Bus)
- MIPI CSI2 Receiver
- Small-size ISP (Image Signal Processing) IP ideal for AI camera systems.
- HDR Image Signal Processor
Related News
- Barco Silex validates interoperable VC-2 lightweight video compression solution for ASIC/FPGA - ready for UHD and 4K transport
- Silex Insight launches DDR encrypter for High-Performing Systems (ASIC/FPGA)
- Introducing superfast serial interfacing with JESD204B Tx - Rx PHY IP Cores in 12nm, 28nm and 40nm for all type of ADC/DAC and ASIC/FPGA connections
- ASICFPGA releases new ISP core supporting AXI4-Lite, AXI4-Stream, new AE, and new AWB
Latest News
- SEMIFIVE Accelerates Growth with 97% YoY Revenue Surge in H1 2026, Powered by ASIC Turnkey, Mass Production, and IP
- Andes Technology has shut down Condor Computing
- TIER IV joins JST’s Next-Generation Edge AI Semiconductor R&D Program to open-source AI chip designs for autonomous driving
- BrainChip Partners With Orama.AOI For AI-Fueled Defect Detection
- PUFsecurity, subsidiary of eMemory, Advances Hardware-anchored Trust for AI Infrastructure at OCP APAC 2026