ASICFPGA releases new advanced Demosaicing core
February 26, 2024 -- ASICFPGA has announced the release of new advanced Demosaicing core, support Multiple Pixel Processing of 1, 2, or 4 pixels per clock. In previous versions of the core, the performance of reducing false color and zipper errors was insufficient. The new advanced demosaicing core can keep high resolution in spite of reducing false color and zipper errors.
Features of new advanced Demosaicing core:
- RGB Bayer image sensor support
- Multiple pixel processing of 1, 2, or 4 pixels per clock
- High quality interpolation
- 8, 10, 12 and 14 bit input and output precision
- Advanced demosaicing algorithm
- Reduced zipper errors
- Reduced false errors
Related Semiconductor IP
- Camera Demosaicing IP (RCCB)
- Image Signal Processor
- Camera Interface (AHB Bus)
- Multiple Pixel Processing Camera Image Signal Processing Core
- MIPI CSI2 Receiver
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