Approaching IP Quality From Many Angles

Ann Steffora Mutschler, Executive Editor
Semiconductor Engineering (October 17th, 2013)

It takes an ecosystem to ensure IP quality. The IP providers, EDA tool vendors and foundries all play a role.

As SoC design complexity has increased, semiconductor design IP and the industry around it has grown in its level of sophistication. This is great news for the users of that IP whose demands for quality, reliability and other deliverables have also been on the rise.

Making sure users have what they need requires close collaboration between the semiconductor foundries, IP providers and of course EDA tool companies. But the engagement of the players in the ecosystem is very different across the spectrum of types of IP, according to Cadence Fellow Chris Rowen because there is an enormous range from subtle high-frequency analog design like PLLs, SerDes, DRAM cells or SRAM cells, etc., which are so intimately tied to the process parameters. This is one end of the spectrum.

At the other end of the spectrum is the pure logic IP where the issues of process dependence are really captured through the libraries. Sometimes those libraries are created in collaboration with the foundries. “You don’t have to talk with the foundries about how their NAND gates work. They just work. Somebody else already sweated that one,” he explained.