AMD's CTO on 7nm, Chip Stacks
Papermaster calls for EUV ASAP
7/24/2017 00:31 AM EDT
SAN JOSE, Calif. — AMD is among chip designers getting an early taste of 7nm process technologies, said its chief technology officer. He called for accelerated work on wafer-level fan-out packaging and greater use of parallelism in EDA software.
To gear up for 7nm, “we had to literally double our efforts across foundry and design teams…It’s the toughest lift I’ve seen in a number of generations,” perhaps back to the introduction of copper interconnects, said Mark Papermaster, in a wide-ranging interview with EE Times.
The 7nm node requires new “CAD tools and [changes in] the way you architect the device [and] how you connect transistors—the implementation and tools change [as well as] the IT support you need to get through it,” he said.
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