Altera casts spotlight on IP integration tool

Altera casts spotlight on IP integration tool
By Crista Souza, EBN
March 7, 2002 (10:32 a.m. EST)
URL: http://www.eetimes.com/story/OEG20020307S0018

To simplify PLD designs that use third-party or home-grown intellectual property, programmable logic suppliers are touting software tools that accelerate IP integration.

This week at the Embedded Systems Conference in San Francisco, Altera Corp. will spotlight SOPC Builder, a tool it created to automate the process of defining, configuring, and linking IP blocks-including multiple processors-to Altera's PLDs, said Bob Garrett, marketing manager for software and tools at Altera's Santa Cruz, Calif., design center.

SOPC Builder reduces the integration process from months to minutes, according to Altera. “At the end of the day, the designer has to be able to put the design together,” Garrett said. “If they're out there hacking away at Verilog or VHDL, they're not getting it done.”

SOPC Builder is designed to allow users to select IP blocks and configure their design parameters using a drop-down list that includes communications, DSP, microproce ssor, and bus interface cores, as well as their own IP. The tool then automatically generates a synthesized netlist, simulation test-bench, and custom software library that reflect the hardware configuration.

Xilinx Inc., San Jose, recently outlined a similar design approach offered by its System Generator tool. The menu-driven application is touted as an essential tool in the design of PowerPC-based Virtex-II Pro parts, but is also considered a valuable design aid for general-purpose complex programmable devices, or what Xilinx calls “platform FPGAs.”

SOPC Builder evolved from Altera's System Builder IP integration tool and was first used in development kits for Nios-processor-based Excalibur devices. Now the company is expanding its use to more general-purpose SOPC designs. The available IP is optimized for Altera's ARM, Nios, and Atlantic products, but the aim is to introduce a wider array of nonprocessor-specific IP, Garrett said.

“The combination of easily accessible IP and a powerful system integration tool is a significant design asset for sophisticated, high-density PLD users and embedded systems designers alike,” said Paul Zorfass, an analyst at IDC, Framingham, Mass.

SOPC Builder is included in the Excalibur Nios Development Kit and Excalibur ARM Solutions Pack, and can be downloaded from www.altera.com. The tool will be integrated in future versions of Quartus II design software.