Aldec offers Tcl/Tk integration tool
Aldec offers Tcl/Tk integration tool
By Richard Goering, EE Times
December 28, 1999 (12:01 p.m. EST)
URL: http://www.eetimes.com/story/OEG19991228S0011
HENDERSON, Nev. Aldec Inc. has rolled out Tool Integrator, a product based on the Tcl/Tk scripting environment that gives users a way to integrate third-party synthesis and implementation tools into its Active-HDL environment. The offering makes it easier for Aldec, which does not offer synthesis, to provide a more complete design environment for programmable logic. Tool Integrator consists of some prewritten Tcl scripts that allow users to invoke third-party tools from within Active-HDL. "You can control your whole design from the Active-HDL environment," said Michael O'Brien, product marketing manager at Aldec. "It's a simplified way to have a GUI call your other tools."
Tcl is a scripting language for launching and controlling external applications. Tk is a graphical user interface tool kit. Tcl/Tk lets users customize design environments with out having to learn proprietary foreign language interfaces. O'Brien said users can download prepared scripts from Aldec's Web site, which support most major FPGA synthesis and layout tools. Users can create their own Tcl/Tk scripts to develop interfaces to other tools.
Once the scripts are installed, the third-party tools can be invoked from the Active-HDL tools menu. When launched, the third-party tools will have their own user interfaces.
Tool Integrator is built into Active-HDL PE (Plus Edition) 3.6, and it supports Tcl/Tk version 8.0. Active-HDL is currently based around VHDL simulation, with Verilog simulation promised for early 2000. There is no additional charge for Tool Integrator. Active-HDL PE prices start at $5,200.
Aldec is also announcing an expansion of its training program for VHDL and Verilog design. The company offers Web-based training, regional language training and on-site training. Aldec also provides free HDL training materials from its We b site.
Related Semiconductor IP
- GPU
- V-by-One Verification IP
- AI model compression IP
- Hardware compressed memory IP for CXL devices and chip-to-chip links
- Hardware link (de)compression IP for die-to-die, chip-to-chip, and DRAM interfaces
Related News
- Aldec Adds Customizable Tool Qualification Data Package to ALINT-PRO for DO-254 Projects
- ALINT-PRO™ Adds New Mixed-Language Design Rules for More Predictable Cross-Language Integration
- Arteris Celebrates 3rd Year of Automotive ISO 26262 TCL1 Functional Safety Compliance for Magillem SoC Integration Automation
- Aldec Announces the Industry’s First Incremental Prototyping™ Methodology
Latest News
- TSMC Boosts 2026 Expansion Budget, Adds $100B to U.S. Investment
- ZeroPoint Technologies Announces ZeroStream
- TSMC Reports Second Quarter EPS of NT$27.25
- Rapidus and Cadence Partner on Agentic AI for Advanced SoC Design
- Defacto’s SoC Compiler Drastically Improved Productivity of L&T Semiconductor Technologies