Alchip collaborates with Synopsys to Address Scale Up and Out Bandwidth Constraints

Collaboration features high-speed SerDes, advanced packaging and SI/PI expertise

SAN JOSE, Calif. -- September 23, 2026 -- Today at the TSMC 2026 North America Open Innovation Platform® (OIP) Ecosystem Forum, Alchip Technologies presented a technical paper with Synopsys on how AI data center ASICs can overcome increasingly stringent bandwidth requirements as scale-up and out interfaces become critical to next generation system architectures. This approach brings together Synopsys 224G PHY IP with Alchip’s advanced packaging and signal integrity/power integrity (SI/PI) expertise in a protocol-agnostic physical design.

Breaking Through the Bandwidth Wall

As AI accelerators scale to meet growing performance demands, moving data on and off the chip fast enough becomes one of the hardest problems in the design. At 224 Gbps SerDes speeds, the presentation addressed several key physical design challenges:

• Die-edge congestion and escape routing complexity, along with signal and power integrity constraints across both die and package
• Limited die-edge real estate and asymmetric constraints between East/West (E/W) and North/South (N/S) edges
• Dense package substrate breakout requirements that must be met without degrading channel performance

The collaboration overcame these barriers through a coordinated optimization of escape routing, die-edge utilization, and package breakout — carefully balancing signal and power integrity requirements to maintain overall system performance. Differentiated handling of E/W and N/S die edges further ensured that maximum bandwidth per millimeter of die-edge beachfront was achieved at max reach, consistently across all die edges.

Building on this work, the analysis extended to E/W package breakout techniques needed to sustain 1.6 terabits per second (Tbps) of networking bandwidth, highlighting key routing density and SI/PI considerations at the substrate level. The resulting protocol-agnostic, forward-scalable physical design approach provides a foundation that can ultimately support 448G SerDes implementations.

Pushing Bandwidth Density to Its Physical Limits

Using this collaborative methodology, engineers achieved chip to chip interconnect bandwidth density approaching theoretical physical limits. This demonstrates the feasibility of ultra high density 224G scale up interconnect implementations within realistic die edge and package constraints.

These results point to broader implications for data center design, as AI accelerators and high performance networking ASICs continue to scale, maximizing bandwidth per millimeter directly impacts system throughput and scalability.

Explore PHY / Serdes IP:

• 224G Ethernet PHY in TSMC (N3E)
• 224G Ethernet PHY for TSMC 3nm

About Alchip

Alchip Technologies Ltd., founded in 2003 and headquartered in Taipei, Taiwan, is a leading global provider of silicon design and production services for system companies developing complex and high-volume ASICs and SoCs. Alchip provides faster time-to-market and cost-effective solutions for SoC design at mainstream and advanced process technology. Alchip has built its reputation as a high-performance ASIC leader through its advanced 2.5D/3DIC design, CoWoS/chiplet design and manufacturing management. Customers include global leaders in AI, HPC/supercomputer, mobile phones, entertainment device, networking equipment and other electronic product categories. Alchip is listed on the Taiwan Stock Exchange (TWSE: 3661).

For more information, please visit our website: http://www.alchip.com