What is 1.25G - 12.5G SERDES?
1.25G - 12.5G SERDES is a Multi-Protocol PHY IP core from Nano Silicon listed on Semi IP Hub.
Vendor:
Nano Silicon
Category:
Multi-Protocol PHY
1.25G - 12.5G SERDES
Key features
- Universal SERDES IP range from 1.25 – 10 Gbit/s
- Half data rate and quadrant data rate support
- 40-bit parallel data bus
- Independent channel power down
- Programmable transmit amplitude and TAP configurable FFE in transmitter
- Build in self test with multiple pattern generation and checking for production test
- Integrated on-die termination resistors
- Receiver detection support
- OOB signal generation and detection support
- Spread Spectrum clock generation (optional) and receive support
- Flexible reference clock frequency, 25 – 156.25 MHz
- Support 1, 2, 4 lanes
- No external component
- ESD: HBM/MM/CDM/Latch Up 2 kV/200 V/500 V/100 mA
Block Diagram
SERDES block diagram
Specifications
Identity
Part Number
SERDES
Vendor
Nano Silicon
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Australia
Frequently asked questions about Multi-Protocol PHY IP cores
How should engineers evaluate this Multi-Protocol PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.