AI Comes to ASICs in Data Centers
eSilicon helped Nervana design its first-gen AI ASIC
Junko Yoshida
6/6/2018 04:01 PM EDT
MADISON, Wis. — Three years ago, when AI chip startup Nervana ventured into the uncharted territory of designing custom AI accelerators, the company’s move was less perilous than it might have been, thanks to an ASIC expert that Nervana — now owned by Intel — sought for help.
That ASIC expert was eSilicon.
Two industry sources independently told EE Times that eSilicon worked on Nervana’s AI ASIC and delivered it to Intel after the startup was sold. eSilicon, however, declined to comment on its customer.
To read the full article, click here
Related Semiconductor IP
- RISC-V Display Connectivity Subsystem (DCS)
- AES-GCM - Authenticated Encryption and Decryption
- AES-GCM Authenticated Encryption and Decryption
- AES-GCM - Authenticated Encryption and Decryption
- Verification IP for C-PHY
Related News
- QuickLogic Announces $1M eFPGA Hard IP Contract for Data Center ASIC
- QuickLogic eFPGA Hard IP Selected by Chipus for 12 nm High Performance Data Center ASIC
- Marvell to Acquire XConn Technologies, Expanding Leadership in AI Data Center Connectivity
- Socionext Collaborates with Arm to Advance AI Data Center Infrastructure with Arm Total Design
Latest News
- Arm delivers record-breaking quarter and full-year results
- SEMIFIVE and ICY Tech Achieve Successful Tape-out of 8nm eMRAM-Based Edge AI SoC, Targeting First Commercialization in Asia
- QuickLogic to Showcase EOS™ S3 and eFPGA Solutions at Sensors Converge
- Rambus Introduces PCIe® 7.0 Switch IP with Time Division Multiplexing for Scalable AI and Data Center Infrastructure
- Siemens hardware-assisted verification validates Arm AGI CPU for scalable agentic AI