AI Comes to ASICs in Data Centers
eSilicon helped Nervana design its first-gen AI ASIC
Junko Yoshida
6/6/2018 04:01 PM EDT
MADISON, Wis. — Three years ago, when AI chip startup Nervana ventured into the uncharted territory of designing custom AI accelerators, the company’s move was less perilous than it might have been, thanks to an ASIC expert that Nervana — now owned by Intel — sought for help.
That ASIC expert was eSilicon.
Two industry sources independently told EE Times that eSilicon worked on Nervana’s AI ASIC and delivered it to Intel after the startup was sold. eSilicon, however, declined to comment on its customer.
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