Ausdia Solves Critical Design Flow Gap with OneSource Constraint Translation at DAC 2025
2025-06-23 17:01:00
EDA & Design Tools
Semiconductor IP News Archive - Page 66 of 1964
Yocto Project Welcomes RISC-V International as New Platinum Member, Expands Global Ecosystem and Leads with Cyber Resilience Act Preparedness
2025-06-23 15:45:00
SoC Architecture & Assembly
Continental to Create an Advanced Electronics & Semiconductor Solutions Organization
2025-06-23 15:26:00
Strategic Partnerships
Arteris Addresses Silicon Design Reuse Challenge with New Magillem Packaging Product for IP Blocks and Chiplets
2025-06-23 13:02:00
EDA & Design Tools
Siemens turbocharges semiconductor and PCB design portfolio with generative and agentic AI
2025-06-23 12:55:00
EDA & Design Tools
Mirabilis Design Signs OEM Agreement with Cadence to Deliver VisualSim for System-Level Modeling and Performance Optimization
2025-06-23 11:32:00
EDA & Design Tools
Rapidus announces collaboration with Siemens for 2nm semiconductor design
2025-06-23 10:19:00
EDA & Design Tools
Caspia Technologies Collaboration to Enhance Security Verification in Siemens' Questa One With Caspia's Generative AI Security Platform
2025-06-23 10:07:00
EDA & Design Tools
True Circuits Announces New and Improved Low-jitter Digital Ultra+ PLL
2025-06-23 07:35:00
IP Cores & Design
True Circuits Introduces the Low-jitter Digital Ultra+ PLL at the Design Automation Conference
2025-06-20 08:26:00
Events & Conferences
Launch of BrainChip Developer Hub Accelerates Event-Based AI Innovation on Akida™ Platform with Release of MetaTF 2.13
2025-06-20 07:54:00
SoC Architecture & Assembly
Agnisys Ignites DAC 2025 with IDesignSpec Suite v9, IDS-FPGA Launch, AI² and IDS-Integrate Enhancements.
2025-06-19 17:36:00
EDA & Design Tools
CAST Launches Multi-Channel DMA IP Core Ideal for Streaming Applications
2025-06-19 10:09:00
IP Cores & Design
ZeroRISC Gets $10 Million Funding, Says Open-Source Silicon Security ‘Inevitable’
2025-06-19 09:11:00
Analysis & Insight
BT Group Joins the CHERI Alliance to Advance Cybersecurity Innovation
2025-06-18 20:54:00
Standards & Interconnects
VESA® Approves Teledyne LeCroy DisplayPort™ 2.1 PHY Compliance Test Specification Software
2025-06-18 19:09:00
EDA & Design Tools
Keysight Enables AMD to Showcase Electrical PCI Express® Compliance up to 64 GT/s
2025-06-18 18:53:00
SoC Architecture & Assembly
Intel Appoints Sales and Engineering Leaders
2025-06-18 16:18:00
People & Leadership
Baya Systems Celebrates First Year of Hypergrowth After Emerging from Stealth
2025-06-18 16:11:00
Strategic Partnerships
Astera Labs and Alchip Announce Strategic Partnership to Advance Silicon Ecosystem for AI Rack-Scale Connectivity
2025-06-18 13:22:00
Strategic Partnerships