3Plus1 Technology Announces Availability of CoolEngine Multicore IP Family for Mobile SoC Products

• Ultra-Low-Power, Low Area Multiprocessor Architecture Used to Create Extensive Range of Audio, Video and Communications Cores for Codec and Modem Implementation in Mobile SoC Designs
• First-Generation Programmable Multicore CoolEngines Scale Beyond H.264 HD in SoC Designs for the Mobile Market Including GPS and BT and GSM

SARATOGA, CA -- October 15, 2007 -- 3Plus1 Technology, Inc. today announced the availability of its first-generation CoolProcessor technology in the form of CoolEngine IP cores for next generation multimedia and communications SoC designs targeting mobile consumer products.

The first instances of the CoolEngine family comprise two members that take advantage of the intrinsic scaling of the 3Plus1 multiprocessor approach for implementation of JPEG, MPEG, H.263, and H.264 encode and decode operations as well as standard audio applications along with GPS and Bluetooth. The company is offering an introductory two-week evaluation program to prospective customers using the CoolEngine development platform.

"We are experiencing very high demand for software-driven solutions for both codec and modem implementations in SoC designs for the mobile market," said Allan Cox, CEO of 3Plus1Technology, "As a result, we are bringing the first generation 'CODEM' CoolEngine cores to market as IP available to leading-edge SoC designers."

Cox went on to add that, "Working with strategic customers, CoolEngine has shown up to 2X area and power advantages over leading 'configurable processor' approaches and shows near-ASIC like efficiencies in a fully programmable architecture."

The first instances of the CoolEngine family are available to evaluation program partners this quarter and are supported by an advanced hardware and software development platform including emulator, compiler, assembler and associated support tools.

"We are supporting customers in the development of software codecs and modems today," said Dr. Amir Zarkesh, 3Plus1 Executive Vice President of Engineering, "and are seeing a groundswell of interest in moving from hardware design to a software programmable solution using scalable multiprocessor technology. System-level modem, i.e. 'CODEM,' implementations in one architecture and the CoolEngine family are designed for this purpose from ground up."

The company continues to market CoolEngines directly to customers in the USA, Europe and South East Asia.

About CoolProcessor

The Company's CoolProcessor technology has been developed in record time, based on an internally developed and automated methodology capable of generating RTL, simulation, analysis, and verification tools from an internal design language for the CoolProcessor Architecture.

The CoolEngine family of cores is scalable and upwardly code-compatible with a single programming model. Development of software applications follows a standard DSP tool flow and the company is currently delivering its initial applications-development software and FPGA Emulator Boards to strategic customers.

About 3Plus1 Technology

Founded in 2003, 3Plus1 Technology has created a design methodology and architectural approach specifically designed for low-power, concurrent execution of specific applications, including MPEG 2/4, H.263/4, JPEG/2000, 802.11 a/b/g/n, 802.16, Bluetooth, UWB, GSM/GPRS/EDGE, CDMA 2000/WCDMA, MP3, AAC, DVB-H and GPS, in a modular, scalable, heterogeneous multiprocessor architecture. The technology enables software implementation of combinations of these multi-mode scenarios and uses models that can be implemented in a sub-100mw processor core in a standard 90nm low power CMOS process.

Financed by its founders since its inception, with additional income from sales of its first tools and services, the company is addressing the needs of the 800-million-plus mobile media player, handset, camera and UMPC markets. 3Plus1 has assembled a group of world-class technologists addressing the problems of real-time voice, video and data processing -- at ultra-low-power levels and minimum silicon die size -- from the fundamental software and hardware architectural perspectives.