H264 ENCODER IIP
H264 Encoder core is compliant with standard ISO/IEC 14496-10/ITU-T H.264 specification.
Overview
H264 Encoder core is compliant with standard ISO/IEC 14496-10/ITU-T H.264 specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices.H264 Encoder IIP is proven in FPGA environment. The host interface of the H264 can be simple interface or can be AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.
H264 ENCODER IIP is supported natively in Verilog and VHDL
Key features
- Supports ISO/IEC 14496-10/ITU-T H.264 specification.
- Supports full H.264/AVC Encoder functionality.
- Supports video resolution up to 3840x2160@60fps.
- Supports all type of prediction methods.
- Inter prediction
- Intra prediction
- Supports profile level up to 6.2.
- Supports precision 8 bits and 10 bits.
- Supports AAC and AC-3 audio Encoder.
- Supports all Chroma type 4:4:4, 4:2:2 and 4:2:0.
- Supports following in VBR encoding mode,
- Rate-Distortion optimized output.
- Output up to 240 MBits/s.
- Supports following in CBR encoding mode,
- On-the-fly rate changes.
- Output up to 240 MBits/s.
- Output Annex B NAL byte stream.
- Supports optional advanced thresholding of quantized transform coefficients.
- Supports run-time tunable operation enables decoder compatibility trade-offs.
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to microprocessor/microcontroller devices
Block Diagram
Benefits
- Single site license option is provided to companies designing in a single site.
- Multi sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
What’s Included?
- The H264 Encoder interface is available in Source and netlist products.
- The Source product is delivered in plain text verilog. If needed VHDL,SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and Linux driver package
- Documentation contains User's Guide and Release notes.
Specifications
Identity
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Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about Video Processing IP
What is H264 ENCODER IIP?
H264 ENCODER IIP is a Video Processing IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this Video Processing?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.