Why Embedded MRAMs Are the Future for Advanced-Node SoCs
Our intelligent, interconnected, data-driven world demands more computation and capacity. Consider the variety of smart applications we now have. Cars can transport passengers to their destinations using local and remote AI decision making. Robot vacuum cleaners keep our homes tidy. Smart watches can detect a fall and call emergency services. With high-volume computations comes greater demand for high memory capacity, along with an absolute necessity to reduce system-on-chip (SoC) power, especially for battery-operated devices.
As data gets generated by more sources, the data needs to be processed and accessed swiftly—especially for always-on applications. Embedded Flash (eFlash) technology, a traditional memory solution, is nearing its end, as scaling it below 28nm is highly expensive. In response, designers of IoT and edge-device SoCs, along with other AI-enabled chips, are seeking a low cost, area- and power-efficient alternative to support their growing appetite for memory.
As it turns out, the new memory solution ideal for low-power, advanced-node SoCs isn’t so new at all. Embedded Magneto-Resistive Random Access Memory (eMRAM) emerged about two decades ago but is now undergoing an uplift in utilization thanks to its high capacity, high density, and ability to scale to lower geometries. In this blog post, we’ll take a closer look at how IoT and edge devices are creating shifts away from traditional memory technologies, why eMRAM is taking off now, and how Synopsys is helping to ease the process of designing with eMRAM.
To read the full article, click here
Related Semiconductor IP
- Chiplet Die-to-Die Interconnect IP Solution
- High speed MACsec Engine 100G/200G/400G/800G/1.6T
- Temperature/Voltage sensors
- AMBA Bus Host to eSPI Controller/Target
- AMBA Bus Host to eSPI Controller
Related Blogs
- Maximizing the Usability of Your Chip Development: Design with Flexibility for the Future
- UEC-LLR: The Future of Loss Recovery in Ethernet for AI and HPC
- Five Architectural Reasons Why FPGAs Are the Ultimate AI Inference Engines
- How Network-on-Chip Architectures Are Powering the Future of Microcontroller Design
Latest Blogs
- Embedded Security explained: Advanced Encryption Standard (AES)
- Cadence Demonstrates PCIe 8.0 PHY at PCI-SIG DevCon 2026
- Cadence Achieves Successful Silicon Validation of 1st IP Test Chips on Intel 18A
- From Classical CAN and CAN FD to CAN XL: Functional Safety and Security for Next-Generation In-Vehicle Communication
- Accelerating Embedded Memory Performance with 16-bit xSPI PSRAM IP