Where Does 5 Really Mean 30? Process Node Naming
November 9, 2015
In my first real blog here, about the Cadence/imec 5nm announcement, I asked what was 5nm on a 5nm process. The answer is nothing. Creating the lithography for 5nm is a major milestone but process naming has become very misleading.
It reminds me of that old Bonzo Dog song Shirt where one little part of the lyrics is:
Good morning. Could I have this shirt cleaned "express," please?
Yes, that'll be three weeks, dearie.
Three weeks? But the sign outside says 59-minute cleaners!
Yes, that's just the name of the shop, luv. We take three weeks to do a shirt.
In the same way “5nm is just the name of the process. It takes 30nm to do the metal.”
To read the full article, click here
Related Semiconductor IP
- DSP-Based 112G SerDes
- XTAL oscillator in TSMC-7nm
- GPU
- V-by-One Verification IP
- AI model compression IP
Related Blogs
- Does RISC-V mean Open Source Processors?
- What Does Fab-Lite Mean?
- What does Cadence mean when it calls System Realization a "holistic" approach to IC design?
- What does Amazon's multiday cloud outage mean for EDA cloud services?
Latest Blogs
- World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects
- One Key for Every Door: How Aliro Extends the UWB Digital Key Beyond the Car
- Reprogrammable Post-Quantum Security for SoCs: Why Crypto-Agility Matters
- Designing the Beam Steering Core for a C-Band AESA: A Look at VSI's VBF0644 GaAs Beamformer IC
- Secure Boot for embedded systems: Building a complete chain of trust