Where Does 5 Really Mean 30? Process Node Naming
In my first real blog here, about the Cadence/imec 5nm announcement, I asked what was 5nm on a 5nm process. The answer is nothing. Creating the lithography for 5nm is a major milestone but process naming has become very misleading.
It reminds me of that old Bonzo Dog song Shirt where one little part of the lyrics is:
Good morning. Could I have this shirt cleaned "express," please?
Yes, that'll be three weeks, dearie.
Three weeks? But the sign outside says 59-minute cleaners!
Yes, that's just the name of the shop, luv. We take three weeks to do a shirt.
In the same way “5nm is just the name of the process. It takes 30nm to do the metal.”
To read the full article, click here
Related Semiconductor IP
- MIL-STD-1553 Controller IP
- UFS 5.x Device IP
- UCIe 3.x Controller IP
- Ethernet 800G PCS IP
- CHI to UCIe Bridge IP
Related Blogs
- Does RISC-V mean Open Source Processors?
- What Does Fab-Lite Mean?
- What does Cadence mean when it calls System Realization a "holistic" approach to IC design?
- What does Amazon's multiday cloud outage mean for EDA cloud services?
Latest Blogs
- CDM Dependence on Device Capacitance
- What the Cyber Resilience Act means for the future of chip design
- When Your IP Vendor Has Operated 150,000 Base Stations: Introducing Viettel Semiconductor
- Relationship between architecture and validation in system design
- The Post-Quantum Cryptography Mandate: Building Cryptographically Agile Systems for the Quantum Era