Verification of Integrity and Data Encryption (IDE) for CXL Devices

By Cadence

September 14, 2023

In continuation of our series on IDE blogs, Why IDE Security Technology for PCIe and CXL? and Verification of Integrity and Data Encryption(IDE) for PCIe Devices, this blog focuses on IDE verification considerations for CXL devices.

With increasing trends of AI, ML, and deep learning in the computing space, there is a focus on security features for SoCs catering to high performance computing (HPC), data analytics, automotive, etc. CXL is rapidly growing as the interconnect of choice for these applications, which does pose security concerns while transmitting mission-critical workloads. Therefore, CXL specification decides to incorporate security IDE features with a similar flow as PCIe IDE. In fact, the operational modus for FLITs transmitted on CXL.io semantics is the same as PCIe.

Coming to CXL.cachemem, AES-GCM is used with 256 key sizes for data encryption and integrity and 96-bit MAC for data protection. However, CXL.cachemem supports only Link IDE. Let’s take a closer look at key verification aspects for CXL.cachemem IDE.

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