TLM: The Year in Review, and Trends for 2012
2011 was my first full year in the land of Transaction-Level Modeling (TLM) design and verification, after spending my entire career to that point in RTL. I made my move upward in abstraction level in mid-2010 because it seemed like the time had finally come for this methodology to start becoming mainstream, delivering the benefits that have been sought for years.
Has this methodology started to become mainstream?
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