The Risks & Rewards of Early Tapeout
July 23, 2014
Verification remains a key issue in system-on-chip development. The time taken to verify a high-density SoC design to a high level of confidence can lead teams to think the unthinkable. One of these counterintuitive options is to not exhaustively verify a chip before taping out but use the resulting silicon itself as a cornerstone of the verification process.
A panel session at the recent 51st Design Automation Conference was more or less evenly split on the approach. Early tapeout has its attractions but carries risks and potential costs that go way beyond the price of a mask set for a device that is highly unlikely to make it to production.
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