Synopsys TileLink Interconnect Verification IP for RISC-V SoCs

By Synopsys, Inc.

January 31, 2023

What is RISC-V?

Reduced Instruction Set Computer Architecture (RISC) is an instruction set architecture (ISA) which implies a basic bridge between hardware and software. RISC enables the communication between an assembly language programmer and a processor by defining a set of simple instructions that are combined to perform various complex instructions.

Both RISC and Complex Instruction Set Computer (CISC) approaches try to optimize a CPU’s processing time. In RISC, cycles required per instruction are reduced while instructions per program are increased. But in CISC, the number of instructions per program are reduced while cycles per instruction are increased.

Execution time = # of instructions per program X # of cycles per instruction

As a result, RISC is more of a software-based ISA as the software must take care of sending necessary simple instructions to execute an application. While CISC is a hardware-based ISA as instruction in CISC is complex and therefore needs complex instruction decoding.

RISC-V is an open standard instruction set architecture based on established RISC principles. Unlike most other ISA designs, RISC-V is provided under open-source licensing, which allows for broad use across the industry.

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