Silicon IP to take over CAE in EDAC results... soon but not yet!
Very interesting results launched by EDAC for Q1 2011, if Computer Aided Engineering (CAE) is still the largest category with $530.6M, the second category is Silicon IP (SIP) with $371.4M, followed by IC Physical Design & Verification at $318.5M. Even more significant is the four quarter moving average results, showing growth in every category, +12.9% for CAE and +7.6% for IC PD & V, but as high as +27.9% for SIP!

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