Power-Efficient Recognition Systems for Embedded Applications
July 12, 2016
eural networks are hot. Las Vegas is hot, too. And there is a connection. In late June, one of the major conferences for the field, Computer Vision and Pattern Recognition (CVPR), is held there. On the Sunday before, Cadence ran a half-day training course on Power-Efficient Recognition Systems for Embedded Applications and I attended it. Trip to Vegas, yeah. Spend all day in a windowless conference room, not so much.
But the whole area is changing really fast with new developments coming all the time. Here are three things that I saw in just the last couple of days:
To read the full article, click here
Related Semiconductor IP
- 1.6T Ultra Ethernet Controller
- Chiplet Die-to-Die Interconnect IP Solution
- High speed MACsec Engine 100G/200G/400G/800G/1.6T
- Temperature/Voltage sensors
- AMBA Bus Host to eSPI Controller/Target
Related Blogs
- ML-DSA explained: Quantum-Safe digital Signatures for secure embedded Systems
- Right Sizing AI for Embedded Applications
- Embedded Security explained: IPsec and IKEv2 for embedded Systems
- Embedded Security explained: Post-Quantum Cryptography (PQC) for embedded Systems
Latest Blogs
- Embedded Security explained: Advanced Encryption Standard (AES)
- Cadence Demonstrates PCIe 8.0 PHY at PCI-SIG DevCon 2026
- Cadence Achieves Successful Silicon Validation of 1st IP Test Chips on Intel 18A
- From Classical CAN and CAN FD to CAN XL: Functional Safety and Security for Next-Generation In-Vehicle Communication
- Accelerating Embedded Memory Performance with 16-bit xSPI PSRAM IP