Power-Efficient Recognition Systems for Embedded Applications
eural networks are hot. Las Vegas is hot, too. And there is a connection. In late June, one of the major conferences for the field, Computer Vision and Pattern Recognition (CVPR), is held there. On the Sunday before, Cadence ran a half-day training course on Power-Efficient Recognition Systems for Embedded Applications and I attended it. Trip to Vegas, yeah. Spend all day in a windowless conference room, not so much.
But the whole area is changing really fast with new developments coming all the time. Here are three things that I saw in just the last couple of days:
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