Paradigm Shift in Semiconductor Industry
September 4, 2014
28nm: Clearly the Last Node of Moore's Law for Most Designs
In our blog 28nm – The Last Node of Moore's Law, we had pointed out that the change has happened, and it is no longer a matter of forecast or prediction. In this blog we will start by reviewing some of what has transpired since that blog, and then focus on the ensuing paradigm shift in the semiconductor industry.
The following chart was presented in the IEEE IITC workshop by Globalfoundries. It illustrates the cost impact of the double patterning required for scaling below 28/22 nm.
To read the full article, click here
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related Blogs
- Keynote: Charting the AI-Powered Transformation in the Semiconductor Industry
- Silicon Valley Must Reinvigorate the Semiconductor Industry
- A Three-Tier Business Model for benefitting the Global Semiconductor Industry
- Paradigm Shift - Semi Equipment Tells the Future
Latest Blogs
- Beyond Trusted: What the NSA’s New Guidance Means for Hardware Security
- A scalable, shader-programmable vector graphics GPU core for low-power MCUs
- Navigating ISO 26262 Part 11: A Guide for Semiconductor Architects
- Embedded Security explained: Digital signatures
- Hardware security verification must go beyond functional testing