Leveraging AI to Optimize the Debug Productivity and Verification Throughput
The impact of semiconductors on various sectors cannot be overstated. Semiconductors have revolutionized our operations from the automotive industry to IoT, communication, and HPC. However, as demand for high performance and instant gratification increases, the complexity of SoCs has grown significantly. With hundreds of IPs integrated into SoCs, bugs have become more common and challenging to fix. The verification process at the SoC level is causing significant delays in tapeout schedules. Detecting bugs within the allocated budget and timeline is becoming increasingly difficult, especially with the reduced geometries and increased gate counts. With SoC design engineers spending more than 70% of their verification time, detecting a single bug takes an average of 16-20 engineering hours. Imagine the impact of having 1000 bugs in a design!
To read the full article, click here
Related Semiconductor IP
- NPU IP
- JPEG XL Encoder
- I2C Master/Slave Controller Core
- NVMe Validation Test Suite
- Hybrid Memory Cube Verification IP
Related Blogs
- The Silent Guardian of AI Compute - PUFrt Unifies Hardware Security and Memory Repair to Build the Trust Foundation for AI Factories
- UA Link vs Interlaken: What you need to know about the right protocol for AI and HPC interconnect fabrics
- Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs
- Pasteur’s Magic Quadrant in AI: The Fusion of Fundamental Research and Practical
Latest Blogs
- Tape-Out Readiness Checklist: Engineering Decisions That Prevent Costly Respins
- How Cadence DSPs Put In-Cabin AI Audio On-Chip in SemiDrive's X10
- The Fastest Path to Scalable Photonic Systems: Using Proven IP for both PIC and EIC designs
- Building Trusted AI Agents from the Silicon Root of Trust
- Heterogeneous Computing in Space