IP-SoC trip report (part II): system level mantra
“IP Innovation is moving from component level to system level”. This mantra was heard during the conference, from various speakers: during the keynote talk by Ganesh R. from Gartner and presentation "Integration-Optimized IP from Cadence" by Ranga Srinivasan, also during discussion around coffee (or a glass of wine, but this was in the evening).
I guess everybody will agree on the principle, somehow it’s like moving from LSI to VLSI 30 or 40 years ago. Cadence’ presentation interest was to clearly state the problem the chip maker involved in SoC design are facing. First, the IP integration costs are the most rising, between Software, Hardware and IP, as it can be seen on Figure 1. In fact, this IP Integration cost has doubled from 2005 to 2010 to reach $5B, and will again doubled to reach $10B in 2014. To make it clear, this is the total cost of ownership for a certain IP, not only the License cost. Within five years (in 2015), it will represent 25% of the total cost to develop a SoC.
To read the full article, click here
Related Semiconductor IP
- Chiplet Die-to-Die Interconnect IP Solution
- High speed MACsec Engine 100G/200G/400G/800G/1.6T
- Temperature/Voltage sensors
- AMBA Bus Host to eSPI Controller/Target
- AMBA Bus Host to eSPI Controller
Related Blogs
- How do you Verify the AMBA System Level Environment?
- Do you have the right 'connection'?
- Between ASIC and microcontroller: It's all about System Realization
- What does Cadence mean when it calls System Realization a "holistic" approach to IC design?
Latest Blogs
- Cadence Achieves Successful Silicon Validation of 1st IP Test Chips on Intel 18A
- From Classical CAN and CAN FD to CAN XL: Functional Safety and Security for Next-Generation In-Vehicle Communication
- Accelerating Embedded Memory Performance with 16-bit xSPI PSRAM IP
- Why nonce reuse can break AES-GCM security in embedded systems
- PQSecure™-Agility Earns NIST CAVP Validation