IEDM: TSMC on 3nm Device Options

By Cadence

January 27, 2020

At IEDM in December, Jin Cai of TSMC presented Device Technology for 3nm Node and Beyond during the short course on Sunday. He divided his presentation up into four parts:

• Historical CMOS scaling trends
• FinFET improvements
• Nanosheet advantages and challenges
• Channel materials beyond Si (Ge, 2D, 1D)

Until about 2000, we were in the era of "happy scaling" where we could use thinner gate oxides, lower voltage, and channel doping to get regular process nodes that were faster than earlier nodes, with higher density, and the same (or lower) power. This was known as Dennard scaling. For the decade after that, we used Hi-K metal gate (HKMG) and strained silicon until we got to 20nm. After that, we switched from planar transistors to FinFETs. Since then, we have needed to use DTCO to add boosters to the process, which also allowed further optimizing of standard cells, such as reducing track counts, using fewer transistors in the FinFETs, self-aligned contact, single diffusion break, contact over active gate, with more in the future.

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