How to Achieve High Bandwidth and Low Latency Die-to-Die Connectivity

By Synopsys, Inc.

June 8, 2021

High-performance computing (HPC) is a hot topic these days, and for good reason. Consider the can containing your favorite soda – countless hours of simulation and engineering work using HPC systems have gone into designing streamlined cans that minimize aluminum waste. Indeed, the benefits of HPC are far-reaching, from its use in mining cryptocurrencies to drug testing, genome sequencing, creating lighter planes, researching space, running artificial intelligence (AI) workloads, and modeling climate change.

Processing massive amounts of data is driving demands for larger and more complex chips at advanced process nodes. What’s more, hyperscalers are transforming the way that data centers are designed and how computing resources are organized. To support their business imperatives of delivering ready access to multimedia resources, fast e-commerce transactions, quick search engine results, and the like, these companies are innovating with new data center architectures—namely, chiplets or multi-die SoC architectures.

In this blog post, I’ll discuss how splitting SoCs into smaller dies for advanced packaging and using die-to-die interfaces to enable high bandwidth, low latency, and low power connectivity can benefit hyperscale data centers. Additionally, I’ll also cover what’s needed to optimize these applications.

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