How the CXL Standard Improves Latency in High-Performance Computing

By Synopsys, Inc.

May 3, 2023

From the dawn of civilization through 2003, roughly five exabytes of data were created in total, according Eric Schmidt, past CEO of Google. By 2025, global data creation is expected to reach 180 zettabytes. This means that within the span of a single generation, we’ve created roughly 36,000 times the amount of data ever created—that’s a lot of data! To accommodate this data explosion, the installed base of storage capacity is expected to increase at 19.2% CAGR through 2025 and the data center accelerator market is expected to grow by 25% CAGR through 2028.

It doesn’t stop there.

Managing data—created, copied, stored, consumed, and otherwise proliferated from the data center to the edge—creates unique challenges for SoC designers. This includes mounting pressure to move the data through systems faster and with greater efficiency and security: Lower power. Smaller area. Lower latency. And with data confidentiality and integrity. It’s essential for the interconnects in multi-die systems to have low latency along with enough flexibility to manage a variety of bandwidths and throughput. Complying with the right industry standards can help ensure design success.

One of the newer kids on the standards block—and quickly gaining traction—is Compute Express Link (CXL), an open interface specification with its own consortium for processors, accelerators, and memory expansion. Read on to learn more about the CXL protocol and when you might want to consider CXL for improving latency in your next SoC design.

What Is the CXL Standard?

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