High-Level Design and Verification: How Can We Finally Move on From the Forrest Gump Era?
Richard Goering wrote an excellent summary of the DAC panel "High Level Synthesis Deployment: Are We Ready?," which can be found here.
His conclusion is that we are getting close, and one of the biggest hurdles still to overcome is the skill set -- the combination of hardware design expertise and C++ -- which represents an opportunity for engineers seeking a new or better career.
That is a very insightful conclusion, given what we see in terms of drivers. Both Eli Singerman of Intel and Mark Johnstone of Freescale pointed out that they cannot accomplish what they need to in terms of design productivity and complexity utilizing RTL-based flows. Referring back to Clem Meas' introduction slide, we are still designing chips using the methodology that came into vogue with Netscape Navigator and Forrest Gump.
To read the full article, click here
Related Semiconductor IP
- TSMC 4nm 3V3 GPIO
- 1 Kbyte EEPROM IP
- 3.6 Kbit EEPROM IP
- AMBA 5 AHB Bus TFT LCD / OLED Display Controller
- AMBA AXI5 / ACE5-Lite TFT LCD / OLED Display Controller
Related Blogs
- Design, Verification, and Software Development Decisions Require a Single Source of Truth
- AI in Design Verification: Where It Works and Where It Doesn’t
- Low-Power IC Design: What Is Required for Verification and Debug?
- How to Shift Left on Low-Power Design Verification, Early and Quickly
Latest Blogs
- Beyond the Fab: Building Europe’s Next Generation of Semiconductor Champions
- AI Semiconductor Design at 3nm and 2nm: Silicon-Proven IP
- Samsung Foundry and Cadence Expand Infrastructure and Physical AI Solution
- Scale-Up Ethernet Ecosystem Ramps Up: Cadence ESUN Controller IP Available
- Advancing Europe’s Automotive Innovation Ecosystem: Arteris Continues Its Work in the RIGOLETTO Project