High-Level Design and Verification: How Can We Finally Move on From the Forrest Gump Era?
Richard Goering wrote an excellent summary of the DAC panel "High Level Synthesis Deployment: Are We Ready?," which can be found here.
His conclusion is that we are getting close, and one of the biggest hurdles still to overcome is the skill set -- the combination of hardware design expertise and C++ -- which represents an opportunity for engineers seeking a new or better career.
That is a very insightful conclusion, given what we see in terms of drivers. Both Eli Singerman of Intel and Mark Johnstone of Freescale pointed out that they cannot accomplish what they need to in terms of design productivity and complexity utilizing RTL-based flows. Referring back to Clem Meas' introduction slide, we are still designing chips using the methodology that came into vogue with Netscape Navigator and Forrest Gump.
To read the full article, click here
Related Semiconductor IP
- Mesochronous Bridge for PCIe/CXL
- AI-native GPU
- OpenGMSL Verification IP
- OpenGMSL Leaf IP
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
Related Blogs
- Design, Verification, and Software Development Decisions Require a Single Source of Truth
- AI in Design Verification: Where It Works and Where It Doesn’t
- Streamline PCIe 6.0 Switch Design with Effective Verification Strategies
- The Integrated Design Challenge: Developing Chip, Software, and System in Unison
Latest Blogs
- Automated, Faster Specification to Sign-Off with IDS-AI
- NovaTech Automation Crius PIU: Bringing Conventional Instrument Transformers onto the IEC 61850 Process Bus
- Single Pair Ethernet and TSN: The In-Robot Network Behind the Next Humanoid Robots
- A design path to success exists for ultra-low-voltage SoCs
- Where Routine Flow Ends Veriest Formal Expertise Begins