HDMI, DisplayPort, MHL IPs + Engineering Team = Good Move
This news is certainly not as amazing that the acquisition of MIPS by Imagination, or Arteris by Qualcomm… but it shows that Cadence is building a complete Interface IP port-folio, brick after brick. The result will be that a complete wall is being built on the Synopsys road to monopoly and complete success on Interface IP market. When evaluating HDMI and DisplayPort IP segment, the two big names are Synopsys and Silicon Image, and Transwitch comes after, quite far from the two leaders. Let’s hope for Cadence that this lagging position was due to a lack of investment, rather than from the quality of the engineering team. In this case, the very strong motivation, and deep pockets of Cadence should help the company to head to head compete with Synopsys in the near future, in this IP market segment where Cadence had so far no product to offer… Thus, we think these asset acquisition will be generate new IP sales for Cadence. If we want to forecast the volume of these IP sales, it can be wise to see the starting point, or what was the latest available business figure for Transwitch.
To read the full article, click here
Related Semiconductor IP
- HDMI
- Verification IP for HDMI
- HDCP 2 on HDMI / DisplayPort Embedded Security Module Firmware (generation 3)
- 4-port Receiver/Transmitter/Repeater HDCP 2.3 on HDMI 2.0 and/or DisplayPort 2.0/1.4 ESM (generation 3)
- 2-port Receiver/Transmitter/Repeater HDCP 2.3 on HDMI 2.0 and/or DisplayPort 2.0/1.4 ESM (generation 3)
Related Blogs
- HDMI vs DisplayPort?... DiiVA is the answer from China!
- Rethinking Display Safety: Why RISC-V-Supervised DisplayPort Subsystems Enable Secure, Isolated Automotive Architectures
- Open-Silicon adds Silicon Logic Engineering - for a good reason
- Abstract Made Concrete: Software Reverse Engineering – Mike McLean of UBM TechInsights Comments on the Bilski Case
Latest Blogs
- Embedded Security explained: Advanced Encryption Standard (AES)
- Cadence Demonstrates PCIe 8.0 PHY at PCI-SIG DevCon 2026
- Cadence Achieves Successful Silicon Validation of 1st IP Test Chips on Intel 18A
- From Classical CAN and CAN FD to CAN XL: Functional Safety and Security for Next-Generation In-Vehicle Communication
- Accelerating Embedded Memory Performance with 16-bit xSPI PSRAM IP